1. Field of the Invention
The present invention relates to field-programmable gate array (FPGA) devices. More particularly, the present invention relates to FPGA devices using Flash memory for programming, and to an efficient segmentation of Flash memory for FPGA applications.
2. The Prior Art
Arrays of flash memory cells for use in FPGA applications are known, and include a plurality of rows and columns of non-volatile memory cells disposed in a plurality of rows and a plurality of columns Each memory cell includes a floating-gate programming transistor and a floating-gate switch transistor sharing its floating gate with that of the programming transistor. A row line is electrically connected to the control gates of each first and second floating-gate transistor in its row. The arrays are divided into a plurality of segments that each include a plurality of rows of memory cells in which the sources of the floating-gate programming transistors in each column are connected to a separate segment source-column line. All of the segment source-column lines are connected to a common source line through source-segment select transistors all controlled by a global read line. The drains of the floating-gate programming transistors in each column of each segment are connected to a segment drain-column line. A master column line is associated with each column in the array. A segment-select transistor is connected between its segment drain-column line and its master column line and is controlled by a segment-select line to connect the segment drain-column line to the master column line. For writing, the segment source lines are connected to the segment drain lines through write transistors controlled by a global write-mode line. Such arrays are found, for example, in products sold under the name “ProASIC3” by Actel Corporation of Mountain View, Calif.